The present invention relates to post decoding of memory circuits generally and, more particularly, to a post decode method and/or architecture for memory circuits using an interdigitated array.
Referring to FIG. 1, a conventional circuit 10 for post decoding of memory circuits is shown. The circuit 10 comprises a plurality of blocks 12a-12n, a global data bus 14, a multiplexer 16 and an I/O circuit 18. Each block 12a-12n presents a signal to an input 20a-20n of the global data bus 14. The global data bus 14 presents a signal to an input 22 of the multiplexer 16. The multiplexer 16 presents a signal to the I/O circuit 18 in response to the signal received at the input 22 and a signal POST_DECODE_ADDR received at an input 24. The I/O circuit 18 presents the signal OUTPUT in response to the signals received from the multiplexer 16.
The blocks 12a-12n comprise an array 26a-26n, a multiplexer 28a-28n and a sense amplifier 30a-30n. The array 26a is connected to the multiplexer 28a. The multiplexer 28a is connected to the sense amplifier 30a and will transfer data in response to the array 26a. The sense amplifier 30a is connected to an input 20a of the global data bus 14 and will transfer data in response to the multiplexer 28a. 
Timing diagrams of the circuit 10 are shown in FIGS. 2a, 2b and 2c. The timing diagrams display the problem of race conditions that occur during operation of the circuit 10. The timing of the signal POST_ADDR is critical to the operation of the circuit 10. FIG. 2a defines a simplified timing diagram for a non-atd variant of device 10. The post decode address input to the multiplexer selects one of two bytes of data from the 16-bit global bus and passes the selected byte to the 8-bit I/O. As an example, a logic low level on post decode address will pass even bits of data, while a logic high level will pass odd bits of data. At some time (i.e., tau) after an address change, the data on the 16-bit global data bus will change to that of the selected address GQ(n). This data then passes through the multiplexer to the I/O. The timing of the post decode address is critical for proper functionality of the device. If the post decode address transitions prior to the global data transition, then the data from address nxe2x88x921, GQ(nxe2x88x921)odd, will be momentarily passed to the I/O. This will cause the outputs of the device to xe2x80x9cglitchxe2x80x9d to the incorrect data. This xe2x80x9cglitchxe2x80x9d is undesirable and can cause performance degradation and excessive noise. Conversely, if the post decode address transitions after the global data transition (FIG. 2b), then the data from address n is properly passed to the I/O. However, the time difference between the global data transition and the post decode data transition (i.e., phi) has a direct adverse impact on the access time of the device. Phi is directly additive to the Taa, or address access time of the device.
FIG. 2c defines a simplified timing diagram for an atd variant of device 10. This type of device generates an atd pulse as a result of an address transition. This atd pulse is used to equalize the data path of the device. As a result, the global data bus is equalized high (or low) during the pulse duration. By necessity the I/O is forced into a high impedance state by the equalized data path. This allows for time during which the post decode address can transition without passing erroneous data to the I/O. The internal post decode address must be positioned within this equalized state in order to avoid the glitches described for the non-atd device.
The present invention concerns an apparatus comprising a first bus, a second bus, a memory and one or more interconnections. The memory may be connected to the first bus and the second bus and may be configured to transfer data over the first bus and the second bus. The one or more interconnections may be connected between one or more data lines of the first bus and the second bus to control a bit-width of the first and second buses.
The objects, features and advantages of the present invention include providing a method and/or architecture that may (i) transform a memory with an internal bus width of N to a device with an external bus width of N/2m using the same base design, (ii) multiplex a single ended data path without inducing unnecessary output data transitions, (iii) have an access time which is not dependent on a post decode address speed, and/or (iv) define post decoding of memories with interdigitated arrays. In one example, the present invention may be used with differential data and a non-interdigitated array.